`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/14 19:04:01
// Design Name: 
// Module Name: RegFile
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Regfile(
    input clk,
    input rst,
    
    input wire [4:0] i_rs,
    input wire [4:0] i_rt,
    input wire [4:0] i_rd,
    input wire i_we,
    input wire [31:0] i_wr_data,
    
    output wire [31:0] o_rs_out,
    output wire [31:0] o_rt_out
    );
    
    reg [31:0] regs [0:31];
    
    assign o_rs_out = i_rs == 0 ? 0 : regs[i_rs];
    assign o_rt_out = i_rt == 0 ? 0 : regs[i_rt];
    
    always @(posedge clk) begin
        if (rst == 0) begin
            regs[0] <= 0;
            regs[1] <= 0;
            regs[2] <= 0;
            regs[3] <= 0;
            regs[4] <= 0;
            regs[5] <= 0;
            regs[6] <= 0;
            regs[7] <= 0;
            regs[8] <= 0;
            regs[9] <= 0;
            regs[10] <= 0;
            regs[11] <= 0;
            regs[12] <= 0;
            regs[13] <= 0;
            regs[14] <= 0;
            regs[15] <= 0;
            regs[16] <= 0;
            regs[17] <= 0;
            regs[18] <= 0;
            regs[19] <= 0;
            regs[20] <= 0;
            regs[21] <= 0;
            regs[22] <= 0;
            regs[23] <= 0;
            regs[24] <= 0;
            regs[25] <= 0;
            regs[26] <= 0;
            regs[27] <= 0;
            regs[28] <= 0;
            regs[29] <= 0;
            regs[30] <= 0;
            regs[31] <= 0;
        end else begin
            if (i_we == 1 && i_rd != 0) begin
                regs[i_rd] <= i_wr_data;
            end
        end
    end
endmodule
